1. Field of the Invention
This invention relates in general to a high linearity, low resolution digital-to-analog (D/A) converter.
2. Description of Related Art
Even though most information, such as sound, temperature, voltage and current, is analog, such information is typically converted into digital representations for manipulation. The reason for the proliferation of digital electronics is found in the fact that analog signals are difficult to manipulate. On the other hand, digital signals can be controlled by simple logic circuits or by microprocessors. Further, the speed and accuracy with which digital signals can be manipulated has led to the advances in telecommunications and computing we are accustomed to today.
Digital-to-analog (D/A) converters (also called DACs) are used to present the results of digital computation, storage, or transmission for graphical displays or for the control of devices that operate with continuously varying quantities. D/A converters are also used in the design of analog-to-digital converters that employ feedback techniques, such as successive-approximation and counter-comparator types. Thus, D/A converters provide the interface between the digital and analog components.
A D/A converter accepts a digital signal in the form of an N-bit parallel data word and converts it to an equivalent analog representation. Several methods have been developed over the years to deal with D/A conversion. Two generally accepted methods are the binary-weighted and binary ladder D/A.
The binary-weighted technique is the oldest and simplest method of converting digital bits into an analog signal. A binary word is applied to a series of gates that drive analog switches which apply weighted-signals to the input of an operational amplifier. The value of the input and feedback resistors are carefully chosen to create a binary progression. Each switch can be closed in combination to generate a predetermined analog output. Since the resistors values range from a very high value for the least significant bit to a very low value for the most significant bit, the binary-weighted method is not practical for applications requiring more than 4 bits of resolution. Thus, the ladder-network technique was developed.
The ladder-network technique is capable of producing binary weighted voltages with only two values of resistance arranged in a type of voltage-divider network known as a binary ladder. The primary advantage of the binary ladder design is its use of only two resistor values.
However, the components providing the input to D/A converters must be matched so that the linearity of the D/A converter and the number of bits provided by the input component are the same. When the linearity requirements of D/A converters exceeds the accuracy to which components can be matched, either the requirements for component matching must be eliminated or matching inaccuracies must be adaptively compensated.
Previously, sigma-delta converters have been used to eliminate matching requirements. In sigma-delta converters, a feedback word is compared to the input word. If the feedback word is greater than the input word, then a unit is subtracted from the feedback word. If the feedback word is less than the input word, then a unit is added to the feedback word. However, the sigma-delta converter has the disadvantage of slow conversion rate and requires filtering to eliminate undesirable noise and/or harmonics generated by the converter.
Pulse width modulation converters have also been used to eliminate the need for component matching. The converter transforms the input word into an analog signal within a predetermined period of time. This period is referred to the conversion period. In a pulse width modulation converter for an N state input word, the conversion period is divided into N-1 subperiods. The converter injects M units to a summer in M of the N-1 subperiods, where M is proportional to the value of the input word being converted.
For N states where the conversion period is subdivided into N-1 subperiods, the injector contributes either 0 or 1 units per subperiod. For a 2 bit word, the number of states is N=2.sup.2 =4 and Tn=Nth time subperiod as indicated in the Table below:
______________________________________ T1 T2 T3 STATE ______________________________________ 0 0 0 0 0 0 1 1 0 1 1 2 1 1 1 3 ______________________________________
This converter has the desirable characteristic that there is only 1 injector which injects multiple times as a function of the input word being converted, and, therefore, does not have the problem of matching multiple components. However, as can be seen from the chart, the amount of signal injected during a single conversion period is not constant, i.e., it can be either 1 or 0 for any given subperiod of the conversion period. This means that the converter creates undesirable noise which must be filtered out if the application is sensitive to such noise.
Reference is made to FIG. 1 which depicts a highly linear pulse generator 2 which emphasizes the need for a high linearity, low resolution converter. The pulse generator implements a .+-.1 and .+-.3 level generator (referred to as 2B1Q generator, i.e. 2 bit to 1 quat generator). If the larger capacitor 4 (C3) is not exactly equal to 3 times the value of the smaller capacitor 6 (C1), then the .+-.3 pulses are not exactly equal to 3 times the .+-.1 pulses. Conventional CMOS processes have capacitor matching on the order of one percent (1%). Therefore, the linearity of a pulse generator 2 as illustrated in FIG. 1 is limited to the capacitor matching of one percent, which results in 40 decibel (dB) linearity.
Thus, it can seen then that there is a need for a D/A converter that will provide high linearity without the problems associated with matching capacitor values.